The present invention relates to a semiconductor device in which a well under the channel of a MISFET is electrically connected to a gate electrode, and a method of manufacturing the same.
Conventionally, to reduce power consumption of a semiconductor device, a power supply voltage Vdd is continuously dropped. However, a threshold voltage Vth of a MISFET is not so largely dropped in order to prevent any increase in OFF-current. Hence, a driving capability (drain current) Id of a transistor tends to be low.
As a device for solving this problem, a DTMISFET (Dynamic Threshold Voltage Metal insulator Semiconductor Field Effect Transistor) has been proposed (Fariborz Assaderaghi, et al, “Dynamic threshold-voltage MOSFET (DTMOS) for Ultra-Low voltage VLSI”, IEEE Trans. Electron Devices, Vol. 44, pp. 414–421, 1997).
The structure of a DTMISFET (DTMOSFET) will be described with reference to FIGS. 26A and 26B. FIG. 26A is a perspective view showing the structure of a conventional DTMISFET. FIG. 26B is a cross-sectional view showing a section taken along a line V–V′ in FIG. 26A. Referring to FIGS. 26A and 26B, reference numeral 3500 denotes an SOI substrate; 3501, an Si substrate; 3502, an insulating layer; 3503, an Si-body (well region); 3504, an n+-type source and drain; 3505, a gate insulating film; 3506, a gate electrode made of polysilicon; and 3507, a p+type diffusion layer serving as a contact to a metal plug 3508 connected to the gate electrode.
A DTMISFET is a MISFET in which the gate electrode and the well (Si-body) under the channel are electrically connected and has an advantage that although a power supply voltage Vdd is low, the driving capability is large, and the OFF current is small. The reason for this advantage is explained by the principle of operation in which the gate voltage is transmitted to the substrate to generate the substrate bias effect, so a threshold voltage Vth is low in the transistor ON state and high in the OFF state.
The device also has the following advantages.
(1) One of reasons why the DTMISFET can realize a high driving capability is that the vertical electric field perpendicular to the channel plane is small, and carrier mobility is large.
(2) The S-factor always has an ideal value of approximately 60 mV/decade (best value at room temperature) in a region where no short channel effect occurs.
(3) A low threshold voltage Vth that is suggested to be unrealizable by a MISFET using a metal gate electrode (e.g., gate using TiN) with a midgap work function can be realized.
However, a DTMISFET has the following disadvantages and therefore is not put into practical use for a long time.
(1) To form the contact area (contact hole and metal plug) connecting between polysilicon gate electrode and the Si-body, the device occupation area increases to result in complex manufacturing process. As shown in FIG. 27, when two contacts for connecting the gate and well region are formed for one transistor, the device occupation area increases. Contact holes are formed on both the left and right sides of the Si-body 3502 to reduce the resistance in the Si-body portion. The same reference numerals as in FIGS. 26A and 26B denote the same parts in FIG. 27, and a detailed description thereof will be omitted.
(2) The high body resistance causes RC delay in the gate wiring, which readily adversely affects the circuit operation.
(3) The source/drain junction capacitance is larger than that of a conventional MOSFET.
(4) A forward bias applied to the p-n junction between the source/drain and the Si-body, and when the power supply voltage Vdd exceeds about 0.7 V, the leakage current increases to make the device unusable.
In recent years, to reduce the p-n junction leakage between a source/drain and an Si-body, an attempt of connecting a gate and body via a capacitor has been proposed (IEEE International Solid-State Circuits Conference Digest of Technical Papers, p. 292, 1997). However, an increase in device area due to capacitor formation poses a serious problem (as described in the above reference, a p-n junction diode also need to be formed when we connect a gate and body via a capacitor).